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From: davidb@inmet.inmet.com
Newsgroups: comp.lang.vhdl
Subject: Re: subprograms with waits
Message-ID: <381900009@inmet>
Date: 13 Mar 91 14:49:00 GMT
References: <144030@<1991Mar12>
Lines: 30
Nf-ID: #R:<1991Mar12:144030:inmet:381900009:000:1142
Nf-From: inmet.inmet.com!davidb    Mar 13 09:49:00 1991


/* Written  9:40 am  Mar 12, 1991 by hughes@eng3.hep.uiuc.edu */

>I have a vhdl entity that contains several copies of the same
>behavioral statements.  These statements contain signal assignments
>and waits.  Is there some way I can group them into a subprogram?  I
>would like to have parameters to the subprogram if possible.

I am not sure what the problem is; I am tempted to answer, "Sure!
Just do it!"

A couple of common errors to avoid:

o The subprogram must be a procedure.  Inout parameters to functions
are not allowed.

o Make sure that the parameter list in the procedure declaration
specifies the class of the parameter as signal.  This is often
omitted, as the class of subprogram parameters is usually defaulted
and the modes usually give enough information as to use.

o Pass all the signals to which you will be assigning values as
parameters.  Inheriting visibility to signals is tricky; the only
place you can really do it is in a process statement.

With these caveats, you should be able to simply drop the process code
into the statement part of the procedure.  Good luck!

						Dave Barton
						barton@i2wash.com