Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!sun-barr!newstop!eastapps!pyrite!sgolson
From: sgolson@pyrite.East.Sun.COM (Steve Golson)
Newsgroups: comp.arch
Subject: Re: Cache Measurement
Message-ID: <4966@eastapps.East.Sun.COM>
Date: 20 Mar 91 17:53:21 GMT
References: <688@spim.mips.COM> <12316@pt.cs.cmu.edu>
Sender: news@East.Sun.COM
Reply-To: sgolson@east.sun.com (Steve Golson)
Organization: Sun Microsystems, Billerica MA
Lines: 32

In article <12316@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
>It would be really nice if mere users, such as moi, could actually
>get measurements from the systems they buy.
>
>In particular, there's no reason why cache control logic couldn't
>keep some software-controlled counters. The SPUR chip had 16 such
>counters, with some 5 modes.
>
>So, what would we want measured?

I worked on a single-chip cache memory for the 80386. We included
three statistics counters that could be software programmed to count
a variety of events:

	Total hits		Write hits		Read hits
	Total misses		Write misses		Read misses
	Total flushes		Write flushes		Read flushes
	Total wait states	Write wait states	Read wait states
	Total accesses		Pipelined accesses	Non-piped accesses
	Elapsed time

Separate counts for instructions and data were not included. Since
this is a modular cache and memory controller, code and data could be
segregated into separate memory banks, and statistics for each could
be gathered from their respective cache controllers.

For more info see "A 2Kbyte Fully-Associative Cache Memory with
On-Chip DRAM Control" by Scott Griffith and Steve Golson, Proc. 1989 CICC.

Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@east.sun.com
       (consultant for, but not employed by, Sun Microsystems)
"As the people here grow colder, I turn to my computer..." -- Kate Bush