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From: mohta@necom830.cc.titech.ac.jp (Masataka Ohta)
Newsgroups: comp.arch
Subject: Re: Second-generation RISC
Message-ID: <7425@titcce.cc.titech.ac.jp>
Date: 20 Mar 91 12:12:48 GMT
References: <6128@baird.cs.strath.ac.uk>
Sender: news@cc.titech.ac.jp
Organization: Tokyo Institute of Technology
Lines: 36

In article <6128@baird.cs.strath.ac.uk>
	gor@cs.strath.ac.uk (Gordon Russell) writes:

>Subject: Re: Second-generation RISC

I think that the only existing second generation RISC is HP's PA-RISC 1.1.

>   Does anyone out their have any additional information concerning the
>PgC7600 microprocessor, other than the overview given by BYTE (March 1991).

I have no information. The other second generation RISC I know is MIPS's
R4000, which in only announced.

>The PgC7600 will reportedly ru at 160 MIPS, a speed made possible
>by integrating numerous support chips into the processor.

I think that the second generaton RISC should:

	1) be faster than 50 MIPS (use whatever reasonable one,
	   absolutely not dhrystone MIPS)

	2) be able to have large (>=0.5Mbyte) cache

	3) have large (>4Gbyte) address space

	4) have FLOPS at least as fast as its external clock.

Moreover, I think they will soon (or already) have dual level cache and
dual level TLB.

I also think that the compilers of the second generation RISC will
be tuned against SPECmark.

Dose anyone have any commnet about the second generation RISC?

							Masataka Ohta