Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!apple!sun-barr!rutgers!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.arch
Subject: Microcomputer Bus Multiprocessing
Keywords: multimasted caching, interrupts
Message-ID: <20037@cbmvax.commodore.com>
Date: 22 Mar 91 01:10:29 GMT
Reply-To: daveh@cbmvax.commodore.com (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 26

I'm looking for references, discussion, flames, whatever on various solutions
to multiprocessing, especially in relation to support for said on microcomputer
buses.

It looks like the typical answer for "who caches what" on a microcomputer is
somewhere between "the host processor is the only thing that can cache" to
"nobody caches any shared memory".  What kind of cache support protocols are
being used, if any.  The only bus I have any reference to that supports any
sort of cache coherency scheme, at the moment, is FutureBus+.  Which would
imply that at the moment, zero microcomputer systems solve this problem.

Along with cache problems, interrupts are another multiprocessor question.  If
a device issues an interrupt, which processor does it go to?  Most systems seem
to be saying "only the host processor".  Pre-Apple NuBus did have a solution
to this problem, but the solution was to simply eliminate normal level 
sensitive, easy to use interrupts.  An I/O device would then generate an 
interrupt by mastering the bus and banging a magic location in the memory map
of the processor of choice.  Sure, it would work, but requiring bus master
capability isn't an easy way to build a $50 serial port card that supports
multiple masters.  Anyone doing it better (again, in the context of a micro).


-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
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	"What works for me might work for you"	-Jimmy Buffett