Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!bywater!arnor!oehler!oehler From: oehler@arnor.UUCP (Rich Oehler) Newsgroups: comp.arch Subject: Re: cache pre-load/no-load instructions Message-ID: <1991Mar22.134858.21847@arnor.uucp> Date: 22 Mar 91 13:48:58 GMT References: <765@ajpo.sei.cmu.edu> Sender: news@arnor.uucp (NNTP News Poster) Reply-To: oehler@ibm.com (Rich Oehler) Organization: IBM T.J. Watson Research Center Lines: 14 In article jonathan@cs.pitt.edu (Jonathan Eunice) writes: |> |> >Does anyone else have them? I seem to recall a posting to the effect that |> >the RS/6000 POWER architecture does not. What about MIPS, SPARC, etc? Is |> >this a me-too feature? |> The RISC System/6000 has cache control instructions, but not touch (to prefetch a line) nor set (to establish a line without fetching). The original 801 (circa 1975) had set and subsequent 801 designs had touch. -- Richard Oehler (oehler@ibm.com)