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From: kds@blabla.intel.com (Ken Shoemaker)
Newsgroups: comp.arch
Subject: Re: Second-generation RISC
Message-ID: <3189@inews.intel.com>
Date: 22 Mar 91 18:33:54 GMT
References: <6128@baird.cs.strath.ac.uk> <7425@titcce.cc.titech.ac.jp>
Sender: news@inews.intel.com
Reply-To: kds@mipos2.intel.com (Ken Shoemaker)
Organization: Santa Clara Microprocessor Division, Intel Corp., Santa Clara, CA
Lines: 41

My personal feeling?  The current generation of RISC processors were defined
given the implementation constraints of at least 5 years ago.  Since then,
the implementation technology has changed considerably.  The number of
transistors you can fit on a chip has grown, of course, but the
disparity of on-chip devices to off-chip devices has grown much more.
Though you can get increased bandwidth by increasing the number of pins
(another development is packages with huge numbers of pins), you have a hard
time pushing the speeds of the interchip interfaces.

But this is just one example of how the technology has changed.  In general,
you can try to adopt existing architectures to the new technology, but you
inevitable create some kind of mismatch which requires more device
complexity to address.  This camp includes both superscaler and
superpipelined implementations of existing architectures, including
implementations of first generation RISC processors.  None of these
implementations can be as clean as the implementation of an architecture which
was designed with the new constraints from the start.  This was one of the
primary reasons for this whole family of processors.  On of the many
possible acronyms that RISC was described to mean even had something to do
with responses to semiconductor technology.

You can even try to expand or generalize your architecture to try to
encompass the new opportunities that a different implementation technology
presents.  But you are still encumbered by the constraints imposed by your
existing architecture.  Which isn't to say that there isn't money to be made
in this camp!  But the closer your architecture it tied to technology, the
better a chance that it will become obsolete when the underlying technology 
changes.

So any "second generation" RISC would necessarily look different than a
first generation RISC in that it would be tuned to a different technology.
Register set sizes might get larger, but my guess is that they would get
smaller and wider.  Multiple execution units would be standard, and would
impose an entirely new set of constraints on instruction sequences.  Delayed
branches will probably go away as they really are an artifact of having a
short, fixed length pipeline.  But my opinion is worth, of course, exactly 
what you paid for it.  I certainly don't want to start a flame war, and I
admit that this may sound like the pot calling the kettle black!
-------------------
Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
	kds@mipos2.intel.com