Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!cs.utexas.edu!asuvax!mcdphx!.UUCP!bobg
From: bobg@.UUCP (Bob Greiner)
Newsgroups: comp.arch
Subject: Re: Microcomputer Bus Multiprocessing
Summary: Proprietary busses for cache coherence
Keywords: multimasted caching, interrupts
Message-ID: <14749@mcdphx.phx.mcd.mot.com>
Date: 22 Mar 91 22:53:34 GMT
References: <20037@cbmvax.commodore.com>
Sender: news@mcdphx.phx.mcd.mot.com
Reply-To: bobg@.UUCP (Bob Greiner)
Organization: Motorola Microcomputer Division, Tempe, Az.
Lines: 24

In article <20037@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes:
>I'm looking for references, discussion, flames, whatever on various solutions
>to multiprocessing, especially in relation to support for said on microcomputer
>buses.

The Motorola Computer Group ships multiprocessors on VMEbus.  The VME141 
is a 68030 board with a write-through cache that supports queued invalidates.  
The VME188 is a 4 processor 88100 board with copy-back cache that supports
cache coherence through retries.  Other boards interact through uncached
memory regions.  

The '188 is not cache coherent versus other cached masters on VMEbus.  It
is internally cache coherent over its proprietary bus.  VME is used as an
IO bus; IO masters that access main memory on the '188 see a hardware-
enforced cache coherent image.  

This technique is used by many other companies: use VME to get to IO, have
a proprietary bus (or switch) with cached processors and main memory.  

This limitation, no cache coherence over the standard backplane bus, is why
I became the author of the cache coherence chapter of Futurebus+.

Bob Greiner, bobg@phx.mcd.mot.com
Not necessarily the opinion of Motorola.