Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!wuarchive!udel!rochester!pt.cs.cmu.edu!gandalf.cs.cmu.edu!lindsay From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay) Newsgroups: comp.arch Subject: Re: cache pre-load/no-load instructions Message-ID: <12463@pt.cs.cmu.edu> Date: 23 Mar 91 19:54:50 GMT References: <20054@cbmvax.commodore.com> Organization: Carnegie Mellon Lines: 17 In article <20054@cbmvax.commodore.com> jesup@cbmvax.commodore.com (Randell Jesup) writes: ::cache pre-load instructions (the compiler inserts these into the ::instr stream, and hopefully, the appropriate cache line will be available ::by the time it's needed, avoiding delays and speeding up single-task ::execution) >Can be fairly effective, especially on a machine with long latencies >and therefore more NOPs to fill in various places. Certain >algorithms can get big wins from this sort of thing. I agree. In particular, ensemble machines (e.g. hypercubes) could find some wins here, because it is their nature to have long-latency accesses. Also, highly parallel algorithms are the most likely to find a use for such features. (They have predictable access patterns, or they access cache-busting quantities of data, or both.) -- Don D.C.Lindsay .. temporarily at Carnegie Mellon Robotics