Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!usc!apple!fernwood!synopsys!craig
From: craig@synopsys.com (Craig Cochran)
Newsgroups: comp.lsi.cad
Subject: Re: Verilog --> FPGA Conversion
Message-ID: <704@synopsys.COM>
Date: 23 Mar 91 02:37:54 GMT
References: <1991Mar22.152417.7186@intellistor.com>
Sender: news@synopsys.com
Organization: Synopsys Inc.
Lines: 24

In article <1991Mar22.152417.7186@intellistor.com> pyle@intellistor.com (Norm Pyle) writes:
>I am looking for information regarding tools to convert (synthesize) Verilog
>HDL to FPGA gates.  The FPGA vendors should be among the market leaders.
>Does anyone know if there are any restrictions put on the HDL because of the
>uniqueness of FPGA architectures? (i.e. is there a Verilog "Style Guide" for
>each vendor?


Gee, what timing.
Synopsys *just* recently announced FPGA support for our logic synthesis tools.
We synthesize Verilog HDL (or VHDL) into Actel, AT&T and TI FPGAs
(in addition to Gate Arrays, Standard Cells, Sea-of-Gates in CMOS, BiCMOS,
ECL, and GaAs technologies from most ASIC vendors).  One other major FPGA
vendor will probably be announced later this year.

For more information, please send me e-mail.  I will summarize to the net
if there is sufficient interest.

-Craig  <craig@synopsys.com>

-- 
Craig Cochran
Product Marketing Manager                email: craig@synopsys.com
Synopsys, Inc.                           voice: (415)962-7723