Path: utzoo!utgpu!cunews!bnrgate!brtph3!brchh104!brchs1!bnr.ca!rice.edu!sun-spots-request
From: pisces!vanroy@ucbvax.berkeley.edu
Newsgroups: comp.sys.sun
Subject: How many cycles to load and store on a SPARCstation?
Keywords: Miscellaneous
Message-ID: <1969@brchh104.bnr.ca>
Date: 18 Mar 91 17:28:00 GMT
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Organization: Sun-Spots
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Approved: Sun-Spots@rice.edu
X-Original-Date: 7 Mar 91 22:21:26 GMT
X-Sun-Spots-Digest: Volume 10, Issue 57, message 5
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I am in the process of retargeting a compiler for the SPARC.  I am
building an instruction reordering stage.  To achieve the best
performance, I need information about the memory system and the pipeline
structure of several implementations of the SPARC.

The machines I am interested in are the SPARCstation 1+ and the
SPARCstation 2.

Does the machine have a cache? If so, what are its characteristics?

What operations will insert a bubble, i.e. a no-op cycle, in the pipe?
For example:

	How many cycles are needed to do a load and a store?
	Is there any advantage (apart from needing only a single instruction
	fetch) to the double-word loads and stores?
	Does using a register the cycle after it is loaded create a bubble?
	Does doing two loads or stores in sequence create a bubble?

Thanks very much,

	Peter Van Roy
	Computer Science Division
	University of California, Berkeley
	vanroy@polaris.berkeley.edu