Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!bellcore!salt!rtm1
From: rtm1@salt.bellcore.com (Ravi Masand)
Newsgroups: comp.sys.transputer
Subject: Transputer's DMA capability: A question
Keywords: Transputer, DMA, Hardware
Message-ID: <321@salt.bellcore.com>
Date: 22 Mar 91 18:34:41 GMT
Organization: Bell Communications Research
Lines: 23




This is a question related to the transputer's
DMA capability. Seems like, when the transputer
gives up the bus (takes MemGranted high) ,
it only tristates the 32 address/data bits leaving
the notMemRd, notMemWr3-0 and notMemS0-4 in their
inactive state. Is this correct ?

This means I have to disconnect them externally
(from  the memory system) to allow a device to
perform DMA.

Anyone know the logic behind this ?? Even the
lowly 68000 and the 8086/88 relenquish the RD/WR
control lines.

Many Thanks

Ravi Masand
rtm1@thumper
201-829-4593