Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: New SPARC definition
Message-ID: <3287@crdos1.crd.ge.COM>
Date: 25 Mar 91 14:50:18 GMT
References: <1991Mar21.185847.27784@elroy.jpl.nasa.gov> <40492@cup.portal.com>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 26

In article <40492@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes:

| The version 8 specification adds integer multiply and divide instructions. 
| In addition, a "Store Barrier" instruction was added that requires all stores 
| initiated before it to be completed before operation can continue. This is 
| designed to support future multiprocessor machines that allow memory 
| operations to occur out-of-order.

  And now we can recycle all the arguments we just had about ordering of
stores to disk.

  "You can't run a database on a machine with out of order {x} writes."

  "But we do."

  "It will be a lot slower because you have to {y}."

  "it's lots faster then then the old {z} machine."

  "Less filling!"

  "Tastes great!"
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
        "Most of the VAX instructions are in microcode,
         but halt and no-op are in hardware for efficiency"