Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!samsung!crackers!m2c!seqp4!jdarcy
From: jdarcy@seqp4.ORG (Jeffrey d'Arcy)
Newsgroups: comp.arch
Subject: Re: Second-generation RISC
Message-ID: <705@seqp4.UUCP>
Date: 25 Mar 91 14:06:40 GMT
References: <6128@baird.cs.strath.ac.uk> <7425@titcce.cc.titech.ac.jp> <3189@inews.intel.com>
Organization: Sequoia Systems Inc., Marlboro, Mass.
Lines: 11

kds@blabla.intel.com (Ken Shoemaker) writes:
>Delayed
>branches will probably go away as they really are an artifact of having a
>short, fixed length pipeline.

As long as there's at least one pipe stage devoted to instruction fetch and
decode, I think delayed branches would make sense.  If this part of the 
pipeline ceases to be fixed length, maybe we'll see multiple-instruction
branch delays, with a *variable* number of instructions after the branch.

ICK!  8]