Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: Second-generation RISC
Message-ID: <3291@crdos1.crd.ge.COM>
Date: 26 Mar 91 16:12:44 GMT
References: <6128@baird.cs.strath.ac.uk> <7425@titcce.cc.titech.ac.jp> <3189@inews.intel.com> <705@seqp4.UUCP>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 15

In article <705@seqp4.UUCP> jdarcy@seqp4.ORG (Jeffrey d'Arcy) writes:

| As long as there's at least one pipe stage devoted to instruction fetch and
| decode, I think delayed branches would make sense.  If this part of the 
| pipeline ceases to be fixed length, maybe we'll see multiple-instruction
| branch delays, with a *variable* number of instructions after the branch.

Sure, if you want a disgusting thought, how about a few bits in the
branch instruction to indicate the number of cycles (minimum) to delay?

This is a truely disgusting thought...
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
        "Most of the VAX instructions are in microcode,
         but halt and no-op are in hardware for efficiency"