Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!uakari.primate.wisc.edu!crdgw1!crdos1!davidsen From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) Newsgroups: comp.arch Subject: Re: Segmented Architectures ( formerly Re: 48-bit computers) Message-ID: <3292@crdos1.crd.ge.COM> Date: 26 Mar 91 16:23:17 GMT References: <1991Mar21.164242.886@sj.nec.com> <23189@as0c.sei.cmu.edu> Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen) Organization: GE Corp R&D Center, Schenectady NY Lines: 22 In article <23189@as0c.sei.cmu.edu> firth@sei.cmu.edu (Robert Firth) writes: | The size of the segment is not the point. The point is that the | physical memory is capable of holding an array of a certain size, | but the addressing scheme won't let you index it. You have only | to hit this problem once in a lifetime, to vow never again to buy | a machine with a segmented address structure. If your domain ever changes from edu to com you will buy what's cost effective, be it segmented, CISC, or threes complement metric tetradecimal. And in some course or other you will probably find that there's a use for a nonlinear addressing scheme sometimes, and that if the segment size is at least as big as max addressible physical memory your argument above is pretty hard to make. The 8086 is not the generic model of segmented addressing, and faults in one implementation are poor starting points to make a case against any idea or method. -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) "Most of the VAX instructions are in microcode, but halt and no-op are in hardware for efficiency"