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From: koll@NECAM.tdd.sj.nec.com (Michael Goldman)
Newsgroups: comp.arch
Subject: Interlocked Pipelines - basic questions
Message-ID: <1991Mar26.171547.2400@sj.nec.com>
Date: 26 Mar 91 17:15:47 GMT
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I have been reading about RISC machines that either do or don't have
interlocking pipelines.  I read also that MIPS, which originally stood for
Microprocessor without Interlocking Pipeline Stages (I think) has introduced
interlocked pipelines.  I am ignorant about interlocking.

1.  What does the interlocking refer to ?

2.  Why is it considered good or bad ?

3.  What, if any, are the implications for interrupt handling ?  (The reason I
    ask is that I will soon be going to a new job which will be using 2 MIPS
    R3000s in a Real-Time system and I wondered if it would be better to
    dedicate one CPU to interrupt handling and the other to applications to
    get the most out of the pipelining for the applications ?)
    
4.  Does this mean MIPS will have to change its name to:
     With Interlocking Microprocessor Pipelined Stages ?  (Forget I said that ;)