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From: piziali@convex.com (Andy Piziali)
Newsgroups: comp.arch
Subject: Re: Second-generation RISC
Summary: The Evans & Sutherland ES-1 used arbitrary delay slot lengths.
Keywords: branch, delay, compare, ES-1
Message-ID: <1991Mar26.215139.9524@convex.com>
Date: 26 Mar 91 21:51:39 GMT
References: <3189@inews.intel.com> <705@seqp4.UUCP> <3291@crdos1.crd.ge.COM>
Sender: Andy Piziali <piziali@convex.com>
Organization: Convex Computer Corporation, Richardson, Tx.
Lines: 12
Nntp-Posting-Host: magnum.convex.com

Regarding arbitrary delay slot lengths, the instruction encoding of the
Evans and Sutherland ES-1 supercomputer specified a bit named the "split bit."
The split bit indicated to the processor to switch the instruction execution
stream from the current stream to the pending branch target stream if the
pending branch was taken.  As with other branch delay slot schemes, the branch
target instruction stream was prefetched between the branch instruction and the
split instruction.
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