Xref: utzoo comp.arch:21667 comp.protocols.nfs:2095 Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!ccu.umanitoba.ca!herald.usask.ca!alberta!cpsc.ucalgary.ca!ctycal!ingoldsb From: ingoldsb@ctycal.UUCP (Terry Ingoldsby) Newsgroups: comp.arch,comp.protocols.nfs Subject: Re: Incremental sync()s and using disk idle time Summary: Even old CPU's can do partial context switch Message-ID: <635@ctycal.UUCP> Date: 25 Mar 91 19:26:11 GMT References: <28975@cs.yale.edu> <1991Mar15.165124.18039@zoo.toronto.edu> Organization: The City of Calgary, Ab Lines: 22 In article <1991Mar15.165124.18039@zoo.toronto.edu>, henry@zoo.toronto.edu (Henry Spencer) writes: > In article <3265@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes: > >Every interrupt will require a context switch in and out of the > >interrupt handler. The only real low cost way to do this is to have a ... > Nonsense. If the handling of the interrupt is sufficiently trivial, > several modern CPUs -- e.g. the 29k -- can do it without a full context > switch, by having a small number of registers dedicated to it. This is It doesn't even have to be modern! Perhaps not as elegant as what you are referring to, but the 8 bit MC6809 used to have a FIRQ (Fast Interrupt Request) in which only a very few registers were saved. This let you take the interrupt, store one or two registers explicitly, do your thing and get back out quickly. -- Terry Ingoldsby ingoldsb%ctycal@cpsc.ucalgary.ca Land Information Services or The City of Calgary ...{alberta,ubc-cs,utai}!calgary!ctycal!ingoldsb