Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hplabs!hpda!hpcuhb!hpcuhe!markw
From: markw@hpcuhe.cup.hp.com (mark williams)
Newsgroups: comp.arch
Subject: Re: Microcomputer Bus Multiprocessing
Message-ID: <32580005@hpcuhe.cup.hp.com>
Date: 26 Mar 91 18:50:16 GMT
References: <20037@cbmvax.commodore.com>
Organization: Hewlett Packard, Cupertino
Lines: 45

The base note asks for references to multiprocessors using microcomputers,
especially in reference to cache coherence and interrupt handling.  
Judging from the poster's address, I think the writer might want a
focused response (limited to MP micros using CISCy or RISCy chips).  I could
respond from that perspective, but I won't.  This subject is is much broader.
The amusing thing for me is that the issues are the same whether the processors
are Am386s(tm) :+) or supercomputers,  so the problem has been studied for
a while.

These topics are very well covered in the literature.  If I were to recommend
just one reference, it would be the excellent tutorial in Computer two years
ago:

   "Synchronization, Coherence and Event Ordering in Multiprocessors", by
   Dubois, Scheurich and Briggs, IEEE Computer, Feb 1988.

There are literally hundreds of other references to pursue, so many that
an annotated bibliography has be done by Eugene Miya   It was posted to
the net recently.  Check your archive.

As for systems, currently dozens of MP systems are shipping, ranging from
PCs (Compaq SystemPro, a dual 486) to Supercomputers (Crays).  They use a wide
range of architectures, from loosely coupled MP (the highly successful Tandem
Computers) to shared memory MP.  

Within the shared memory camp, which has the most implementations, all the
vendors I know of use a proprietary processor/memory bus and most couple to
some standard bus like VME or EISA to leverage low-cost I/O controllers.  
The processor/memory bus maintains cache-coherence, which the standard I/O
buses cannot do (without proprietary extensions).  

This leads to some tricky problems extending locks to I/O
space with acceptable performance.  Cache-coherence over I/O space can be 
implemented in the bus converter between the processor/memory bus and the
I/O bus.  This too is tricky.

In an earlier post, Futurebus+ was mentioned as a potential solution, since
it is a "standard bus" with a defined cache coherence scheme.  Whenever the
"standard" gets approved (and frozen), it's worth taking a look at.  At least
one major vendor has plans to use Futurebus+ as a standard I/O bus, because
it's faster than other current "standard" I/O buses.

Disclaimer:  Just one man's opinion.

Mark Williams