Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!cs.utexas.edu!sun-barr!newstop!texsun!convex!news
From: krolnik@convex.COM (Adam Krolnik)
Newsgroups: comp.arch
Subject: Re: Second-generation RISC
Summary: PIPE and WISQ also had variable branch delays
Message-ID: <1991Mar27.163745.12355@convex.com>
Date: 27 Mar 91 16:37:45 GMT
References: <3189@inews.intel.com> <705@seqp4.UUCP> <3291@crdos1.crd.ge.COM>
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Reply-To: krolnik@convex.COM (Adam Krolnik)
Organization: Convex Computer Corporation, Richardson, Tx.
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Two interesting architecture papers

WISQ: A Restartable Architecture using Queues
   and
PIPE: A VLSI Decoupled Architecture


Both of these had a count of instructions that were the delay slot.

Pipe: had a count that specified the number of instructions to execute regardless of the
outcome of the branch.

Wisq: had a mask that specified which instructions to invalidate, if the processor predicted the
wrong path to execute.



      Adam Krolnik
      Design Verification Engineer  214-497-4578
      Convex Computer Corp. Richardson, Tx 75080