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From: ddr@cs.edinburgh.ac.uk (Doug Rogers)
Newsgroups: comp.arch
Subject: Re: Microcomputer Bus Multiprocessing
Keywords: multimasted caching, interrupts
Message-ID: <8227@skye.cs.ed.ac.uk>
Date: 25 Mar 91 18:05:49 GMT
References: <20037@cbmvax.commodore.com>
Sender: nnews@cs.ed.ac.uk
Reply-To: ddr@cs.edinburgh.ac.uk (Doug Rogers)
Organization: Department of Computer Science, University of Edinburgh
Lines: 33

In article <20037@cbmvax.commodore.com>, daveh@cbmvax.commodore.com (Dave Haynie) writes:
> I'm looking for references, discussion, flames, whatever on various solutions
> to multiprocessing, especially in relation to support for said on microcomputer
> buses.
> 

> .............  The only bus I have any reference to that supports any
> sort of cache coherency scheme, at the moment, is FutureBus+.  Which would
> imply that at the moment, zero microcomputer systems solve this problem.

Apart from specialist in house busses like those used by Sequence
> 
> Along with cache problems, interrupts are another multiprocessor question.  If
> a device issues an interrupt, which processor does it go to?  Most systems seem
> to be saying "only the host processor". 

Futurebus supports interupts through its message passing scheme, the distributed
arbitration mechanism goes to two passes, the first showing a message is being
sent that wins over arbitrators for the bus, and the second pass of the protocol 
places the message on hte bus. It is up to the other arbiters to recognise 
messages that are intended as interupts locally. Some messages are reserved for 
powerdown etc.

There are 3 agreed profiles for futurebus, which all might be a bit heavy for 
small personal machines. New profiles are being put forward for such machines,
if you are interested why not contact someone on the  IEEE 896 working
group.

-- 
Douglas Rogers                     JANET: ddr@uk.ac.ed.lfcs
Department of Computer Science     UUCP:  ..!mcvax!ukc!lfcs!ddr
University of Edinburgh            ARPA:  ddr%lfcs.ed.ac.uk@nsfnet-relay.ac.uk
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