Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hplabs!hpl-opus!hpnmdla!darrylo
From: darrylo@hpnmdla.hp.com (Darryl Okahata)
Newsgroups: comp.arch
Subject: Re: Snake
Message-ID: <7410003@hpnmdla.hp.com>
Date: 27 Mar 91 02:53:51 GMT
References: <69465@brunix.UUCP>
Organization: HP Network Measurements Div, Santa Rosa, CA
Lines: 21

In comp.arch, linley@hpcuhe.cup.hp.com (Linley Gwennap) writes:

> (Curtis Yarvin) asks:
> > Does anyone know how these numbers were achieved?  Are they misleading in
> > any way?
>
> Yes, they are misleading.  The performance on real applications (not
> toy benchmarks) is actually significantly *higher* due to the much larger
> caches (128KB I/256KB D) than competing systems.

     I'd like to point out that the D-cache is 64-bits wide, to improve
floating-point performance.  The I-cache is only 32-bits wide, and comes
in either 128K or 256K configurations.

     -- Darryl Okahata
	UUCP: {hplabs!, hpcea!, hpfcla!} hpnmd!darrylo
	Internet: darrylo%hpnmd@relay.hp.com

DISCLAIMER: this message is the author's personal opinion and does not
constitute the support, opinion or policy of Hewlett-Packard or of the
little green men that have been following him all day.