Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: Memory hierarchy (was: Snakebytes)
Message-ID: <3300@crdos1.crd.ge.COM>
Date: 28 Mar 91 16:17:06 GMT
References: <1998@kuling.UUCP> <2832@shodha.enet.dec.com>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 22

In article <2832@shodha.enet.dec.com> devine@shodha.enet.dec.com (Bob Devine) writes:

| My questions are to the folks with a /dev/crystal_ball: when will
| two level processor caches be here?  When will a storage hierarchy
| be extended to disks (or to ram-disk, or ... etc)?

  You don't need the hardware assist to answer this one, you can do it
with no balls at all. NOW.

  The intel 486 has the pipeline, on chip cache, off chip cache, main
memory, and virtual memory. That's multilevel by any definition.

  Companies like Epoch have fileservers now which do caching, using
many MB of memory, then a GB or so of hard disk, and ending with 30GB
or so of optical. There are other companies doing it, too, and I think
Plexus (the software reincarnation) is doing something like this on a
portable basis.

-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
        "Most of the VAX instructions are in microcode,
         but halt and no-op are in hardware for efficiency"