Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!cs.utexas.edu!natinst!uudell!perform.dell.com!samf
From: samf@perform.dell.com (Sam Fuller)
Newsgroups: comp.arch
Subject: Re: Snake
Message-ID: <17274@uudell.dell.com>
Date: 28 Mar 91 17:37:33 GMT
References: <69465@brunix.UUCP> <7410003@hpnmdla.hp.com>
Sender: news@uudell.dell.com
Reply-To: samf@perform.dell.com (Sam Fuller)
Organization: Dell Computer Corp.
Lines: 22

In article <7410003@hpnmdla.hp.com>, darrylo@hpnmdla.hp.com (Darryl Okahata) writes
  
|>      I'd like to point out that the D-cache is 64-bits wide, to improve
|> floating-point performance.  The I-cache is only 32-bits wide, and comes
|> in either 128K or 256K configurations.
|>

What does that mean? I assume a cache line is wider than 4 or 8 bytes.  Is this
the width of the processor to cache bus for I and D respectively?

Sam Fuller
Dell Computer
Advanced Systems 
samf@perform.dell.com
 
|>      -- Darryl Okahata
|> 	UUCP: {hplabs!, hpcea!, hpfcla!} hpnmd!darrylo
|> 	Internet: darrylo%hpnmd@relay.hp.com
|> 
|> DISCLAIMER: this message is the author's personal opinion and does not
|> constitute the support, opinion or policy of Hewlett-Packard or of the
|> little green men that have been following him all day.