Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!snorkelwacker.mit.edu!bloom-beacon!eru!hagbard!sunic!mcsun!corton!laas!jenn
From: jenn@laas.laas.fr (Eric Jenn)
Newsgroups: comp.lang.vhdl
Subject: VHDL and System Level Simulation
Keywords: system level simulation
Message-ID: <5508@laas.laas.fr>
Date: 26 Mar 91 12:38:08 GMT
Sender: news@laas.laas.fr
Organization: LAAS/CNRS France
Lines: 19

This will probably looks like a dumb question, but ...

I'm interested by the VHDL language in the framework of system level
simulation. By "system level", I mean  tasks scheduling,  synchronization and
communication between tasks  etc...
 Of course, there are many simulation languages specialized in system level
simulation (GPSS, SIMSCRIPT, SES, CADAS etc...), but most of them are unable to
model low level (gate or RTL)  behaviors easily .
Therefore, choosing one of these languages is a choice that limits ***  a
priori *** the depth (and therefore  the accuracy) of our analysis.
From this point of vue, VHDL seems to be a good choice IFF it provides the
features able to model (more or less easily) the kind of mechanisms we meet in
system level simulation.
So the real question is :
"is VHDL  sufficiently powerful to be a hardware description language AND a
system level simulation language ?"
Any advice or information ?
Thanks a lot ...
Eric