Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!caen!uflorida!mlb.semi.harris.com!trantor.harris-atd.com!wookie!jes From: jes@wookie.ess.harris.com (Jim Stroud) Newsgroups: comp.lang.vhdl Subject: Do you like using VHDL for synthesis ??? Message-ID: Date: 26 Mar 91 13:55:18 GMT Sender: news@trantor.harris-atd.com Reply-To: jes@wookie.ess.harris.com Lines: 25 We are starting our first VHDL synthesis project and I do not have a warm feeling regarding the suitability of VHDL for syn- thesis. This design is a ~30k gate digital frame analyzer employing a complicated synchronous state control function operating at 500 Mhz (GaAs/ECL ASIC). It doesn't seem like the VHDL code to implement this design reveals the spirit of the design. It seems that when I look at VHDL RTL descriptions, I am so overwhelmed by the volume of VHDL syntax and underwhelmed by the amount of "my design". This is a pilot project for our division. I can't help but think that the Verilog description of this design would be more concise and less "over/underwhelming". If anyone has a comment regarding this, please respond. -- ISD ==> moving Milestones wherever possible -- -- James (JIM) Stroud jes@wookie.ess.harris.com | "... This ain`t no upwardly mobile freeway ... Harris Corporation - GOV INFO SYS DIV | Oh no ... This is the ROAD TO HELL ..." P.O. POX 98000 Melbourne, FL 32902 | - Chris Rhea (407) 984-5673 (407) 984-5652 | GISD - "Home of the `Mobile Milestones'"