Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uwm.edu!src.honeywell.com!farragut!carpent From: carpent@SRC.Honeywell.COM (Todd Carpenter) Newsgroups: comp.lang.vhdl Subject: Re: Do you like using VHDL for synthesis ??? Message-ID: <1991Mar26.193452.10940@src.honeywell.com> Date: 26 Mar 91 19:34:52 GMT References: Sender: news@src.honeywell.com (News interface) Organization: Honeywell Systems & Research Center Lines: 66 In-Reply-To: jes@wookie.ess.harris.com's message of 26 Mar 91 13:55:18 GMT Nntp-Posting-Host: farragut.src.honeywell.com YES. I LIKE VHDL FOR SYNTHESIS. Jim> This design is a ~30k gate digital frame analyzer employing Jim> a complicated synchronous state control function operating at Jim> 500 Mhz (GaAs/ECL ASIC). It doesn't seem like the VHDL code Jim> to implement this design reveals the spirit of the design. Jim> It seems that when I look at VHDL RTL descriptions, I am so Jim> overwhelmed by the volume of VHDL syntax and underwhelmed by Jim> the amount of "my design". This is a pilot project for our Well, I should really not post this. Be prepared to be offended, since this is rather inflammatory. I've had to battle this misconception far too many times. With that in mind... Those RTL descriptions you saw were probably poorly written by somebody that didn't know a whole heck of a lot about VHDL. Or were a marketing ploy by Verilog (or some other language) people, or produced by some wonderful "translator". NEVER rely upon a translator to produce readable code. I can write VHDL descriptions just as concisely as I can write Verilog. Okay, I lied. I might have to use the word OR instead of |. But really, which one is easier for other people (especially someone not familar with the language) to read? I can also write incredibly verbose, illegible Verilog. I can even write VHDL with one character variables, alias things, and make it look like FORTRAN! Or, I can use a well documented, GNU Emacs supported (or other syntax irected editor supported) VHDL style that encourages good use of indentation, capitalization guidelines, and naming conventions. I can also use packages to hide complexity from both the synthesizer and the designers. It is all a matter of education and skill. The other thing you might examine more closely is the functionality of those VHDL RTL models. You could find there are many more checks for S/H violations, and other things already imbedded in the code. In other words, those verbose models you saw might have been written by a good VHDL designer, who was trying to make the models perform useful functions. Jim> division. I can't help but think that the Verilog description Jim> of this design would be more concise and less "over/underwhelming". If you have poor VHDL writers, and dedicated, trained, and well payed Verilog writers, then I guess this might be a valid statement. If you have two groups of equally skilled people, one doing Verilog the other VHDL, my guess is that you'd probably (short term) be happy with both of their results. Of course, 4 years from now when you expect to run the latest whizzbang tools on the model, to perhaps bring it to the latest and greatest technological level (like automatic partitioning, resource sharing, and automatic insertion of fault handling capabilities), you'll be much happier with the 1000:1 ratio of new VHDL tools. Other issues, such as strong typing, an LRM, ease of debugging, symbolic debuggers, multiple vendors (i.e., lots of competition), multi level support, and government requirements to use VHDL might also be factored in. But you probably knew that. Sorry if I ticked anyone off. Feel free to continue this via email. I'd be happy to post a final summary. -TC Todd P. Carpenter Honeywell Systems and Research Center (612)782-7229 3660 Technology Drive, Minneapolis, MN 55418-1006 carpent@src.honeywell.com or Arkon%kryl@src.honeywell.com !srcsip!carpent Citadel: US 612 699 3106 (Kryl) User Manual, p34, line 5: I am not authorized to have any opinions.