Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!snorkelwacker.mit.edu!bloom-beacon!eru!hagbard!sunic!news.funet.fi!ousrvr!ousrvr!jukka From: jukka@tk4.oulu.fi (Jukka A. Lahti) Newsgroups: comp.lang.vhdl Subject: Re: VHDL and System Level Simulation Message-ID: Date: 26 Mar 91 19:29:49 GMT References: <5508@laas.laas.fr> Sender: news@ousrvr.oulu.fi Organization: University of Oulu, Dept. of EE, Finland Lines: 23 In-reply-to: jenn@laas.laas.fr's message of 26 Mar 91 12:38:08 GM In article <5508@laas.laas.fr> jenn@laas.laas.fr (Eric Jenn) writes: > So the real question is : > "is VHDL sufficiently powerful to be a hardware description language AND a > system level simulation language ?" In my experience, it is. It has all the power you need, if you just have the patience to write all that code. We have been using VHDL for high level system modelling for some time, and come to the conclusion that you definitely need a graphical method (with well defined semantics) and tool to generate the VHDL models for you. We have developed some tools that generate behavioural VHDL code from graphical Structured Analysis (SA) data-flow and state-transition diagrams. I think this is the way to go, if you don't want to spend all your time writing port- and component declarations etc. - jukka -- ------------------------------------------------------------------------ Jukka Lahti (jukka@steks.oulu.fi) Phone: +358-81-352756 University of Oulu, Electronics Lab. Telefax: +358-81-561278 SF-90570 Oulu, FINLAND