Path: utzoo!utgpu!news-server.csri.toronto.edu!qucdn!wooa
Organization: Queen's University at Kingston
Date: Thursday, 28 Mar 1991 16:03:50 EST
From: <WOOA@QUCDN.QueensU.CA>
Message-ID: <91087.160350WOOA@QUCDN.QueensU.CA>
Newsgroups: comp.lang.vhdl
Subject: RE: High level modelling in VHDL

Eric Jenn (jenn@laas.laas.fr) writes:

>  So the real question is :
>  "is VHDL sufficiently powerful to be a hardware description language AND a
>  system level simulation language ?"

Jukka Lahki (jukka@tk4.oulu.fi) replied:

>  In my experience, it is ... you definitely need a graphical method ...

I agree with Mr. Lahti in that a graphical interface is the preferred
entry mode into VHDL.  But I would say from my work that VHDL is not
powerful enough to simulate high level modelling paradigms.  I have
tried to translate Petri nets and statecharts (developed by David Harel)
into VHDL and found it too restrictive.  For instance, Petri nets are
intrinsically non-deterministic and VHDL cannot simulate random ordering
of processes.  VHDL also lacks complete process control need to stop, suspend,
restart processes, a feature required by statecharts.

I would be interested to know if anyone else is working on high level
modelling in VHDL.

Thanks in advance,

    Arthur Woo
    Queen's University
    Kingston, Ontario, Canada
    woo@eleceng.ee.queensu.ca