Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!cs.utexas.edu!uunet!cadence!rookie!dave
From: dave@rookie.cadence.com (Dave Rich; x6337)
Newsgroups: comp.lsi.cad
Subject: Re: verilog query
Message-ID: <1991Mar24.171323.6961@cadence.com>
Date: 24 Mar 91 17:13:23 GMT
References: <1991Mar21.172926.2755@hoss.unl.edu>
Sender: usenet@cadence.com (USENET News)
Reply-To: dave@rookie.cadence.com (Dave Rich; x6337)
Organization: Cadence Design Systems, Inc.
Lines: 29

Here is a copy of the announcement that was posted on usenet a few months ago

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I have started a new reflective mailing list to discuss the Verilog
Hardware Description Language.  Cadence opened the Verilog Language
to the public this year, and will hand over control of the language
to a steering committee.  

This mailing list will help focus discussion about the Verilog language
and can also let users swap tricks and ask each other questions.

The list is implemented as an unmoderated reflector.  It currently has
people from Sun, Encore, Prime and several other sites. Cadence's
Verilog engineers are on the list as well as me, the Verilog/PLI
technical specialist.

Here are the addresses:

The List         -  verilog@cadence.com
To Join or Leave -  verilog-request@cadence.com

This list will be the best place to enter your views on where Verilog should
go, or to find the answers to tricky Verilog questions.  If the traffic
get's large enough it may grow into a newsgroup (comp.lang.verilog?)

Enjoy the list!

Ray Salemi
rays@cadence.co