Newsgroups: comp.os.minix
Path: utzoo!utgpu!cunews!bnrgate!bmerh408!bmerh451!dgraham
From: dgraham@bmerh451.bnr.ca (Douglas Graham)
Subject: Re: Patches to PC MINIX and splitting this group
Message-ID: <1991Mar28.221645.20746@bmerh408.bnr.ca>
Sender: news@bmerh408.bnr.ca (Usenet News Admin)
Organization: Bell Northern Research, Ottawa, Canada
References: <4177@rwthinf.UUCP> <786@philica.ica.philips.nl>
Date: Thu, 28 Mar 91 22:16:45 GMT

In article <786@philica.ica.philips.nl> adrie@beitel.ica.philips.nl (Adrie Koolen) writes:

>On a Sparc-
>Station it's somewhat slower, the Sparc processor has 120 32-bit general
>purpose registers and also 32 floating point registers have to be saved
>when the interrupted process uses them.

Yow!  That's a lot of register saving.  I thought that one of the neat
features of the SPARC architecture was it's register windows.  As long
as there is a window of (16?) registers available when an interrupt
occurs, no registers need to be saved at all by the ISR.  And as long
as the ISR doesn't use the FPU, there shouldn't be any need to save
floating pointing registers.

'course for a full context switch, you'd have to save all registers.
I guess the problem is that Minix does a full context save and restore
in response to an interrupt, even if all the ISR wants to do is
grab a character from the UART, stuff it into a buffer, and then return
to the interrupted process.
---
Doug Graham   dgraham@bnr.ca   Bell-Northern Research, Ottawa Ontario Canada