Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!uwm.edu!csd4.csd.uwm.edu!markh
From: markh@csd4.csd.uwm.edu (Mark William Hopkins)
Newsgroups: comp.os.msdos.programmer
Subject: Re: interrupt priorities/swapping
Message-ID: <10586@uwm.edu>
Date: 28 Mar 91 23:39:15 GMT
References: <1991Mar19.131959.8841@uwovax.uwo.ca>
Sender: news@uwm.edu
Organization: University of Wisconsin - Milwaukee
Lines: 25

In article <1991Mar19.131959.8841@uwovax.uwo.ca> bangarth@uwovax.uwo.ca writes:
>Where can I find a good discussion on interrupts?

Here. :)

From highest to lowest:
   Divide Overflow (INT 0),
   INT n,
   INTO (which is the overflow interrupt = INT 4),
   NMI (non-maskable interrupt = INT 2)
   External interrupt on INTR line (INT 8 to INT f (hex)).
   Single-step interrupt (INT 1).

INTR's ultimately come from hardware lines on the system board (Timer = 8,
Keyboard = 9, (a is reserved), COM2 = b, COM1 = c, Disk = d, Diskette = e,
Printer = f) and are called respectively interrupt requests (IRQ) 0 to 7.

NMI normally comes from the system board and marks a critical system board
error (unless the manufacturer abuses this intended purpose of NMI).

Divide by zero comes from the chip itself during a divide instruction.

I believe that if any of these interrupts are called from software with
an explicit INT n instruction then they are treated priority-wise as INT n,
regardless of the special meanings they may otherwise carry.