Xref: utzoo comp.sys.3b1:861 unix-pc.general:7562
Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uwm.edu!linac!att!ucbvax!ucdavis!csusac!unify!longbow!ttank!fbits!Mariusz
From: Mariusz@fbits.ttank.com (Mariusz Stanczak)
Newsgroups: comp.sys.3b1,unix-pc.general
Subject: Hardware freaks Unite (on this one)
Keywords: 3B1, cache, hardware project suggestion.
Message-ID: <95@fbits.ttank.com>
Date: 23 Mar 91 21:58:06 GMT
Followup-To: comp.sys.3b1
Organization: Forth Bits
Lines: 28

No offence to the Subject, but I just finished "reading" 
an interesting article in Electronic Design (USSN 0013-4872,
Vol 39, No. 5, March 14 1991, page 59) entitled Upgrade a
68030-Based System With a Clever Cache Design.
The article outlines how to build and add to an existing
system (i.e. no changes to architecture) a cache controller
doughterboard with 5 chips (two cache comparators and three
PALs) plus 8 static RAM chips that (on the 68030) gives
a theoretical 29% speedup.  I can bearly follow traces, and
read signal names, but it appears that all (similar ;-))
signals that this project uses are on the 68010, SO maybe
the brave-at-heart-hardware-types would be interested at
looking into the feasibility of transfering the idea to the
3B1 hardware?  Involved project no doubt, but if possible,
it'd be a safe way to boost performance of the system (as
opposed to trying to fit a more efficient processor and
making the OS angry ;-)).

Lights off,

-Mariusz

P.S.	I'd be happy to send photocopies to anyone interested
	in pursuing the thought.
-- 
INET: Mariusz@fbits.ttank.com
CIS : 71601.2430@compuserve.com
UUCP: ..!uunet!zardoz!ttank!fbits!Mariusz