Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!uunet!glyph!ahh
From: ahh@glyph.kingston.ny.us (Andy Heffernan)
Newsgroups: comp.sys.3b1
Subject: Re: 3b1 add-on boards **REPOST**
Message-ID: <1592@glyph.kingston.ny.us>
Date: 26 Mar 91 01:45:07 GMT
References: <1991Mar16.211250.7736@texrex.uucp> <1991Mar19.023406.20620@i88.isc.com>
Reply-To: ahh@glyph.UUCP (Andy Heffernan)
Organization: Moji Computing
Lines: 21

In article <1991Mar19.023406.20620@i88.isc.com> botton@i88.isc.com (Brian D. Botton) writes:
->>This article never showed up on my machine at work so I am reposting it. 
->>Sorry if you already saw it.
[...]
->>Hardware hackers,
->>
->>Why don't you have to set Interrupt Request vectors on boards
->>for the 3b1 like you do on boards added to PCs.  Is this just 
[...]
->  Basically, of the 7 possible interrupt levels on a 680x0, level 1 and 5 are
->shared with all expansion cards, with level 5 being the highest.  The philsophy
->of the 3B1 expansion bus is to never have to set jumpers, all boards are self
->configuring.  This is what they (AT&T) does with their switching equipment.

More basically, isn't it true that things like interrupt request
vectors flying into the processor from interrupting devices is
an Intel-ism?  Motorola-style memory-mapped I/O doesn't do that.

-- 
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  Andy Heffernan		$BJ8;z(J		uunet!glyph!ahh