Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!apple!motcsd!mcdcup!mcdchg!laidbak!botton
From: botton@i88.isc.com (Brian D. Botton)
Newsgroups: comp.sys.3b1
Subject: Re: Hardware freaks Unite (on this one)
Keywords: 3B1, cache, hardware project suggestion.
Message-ID: <1991Mar26.023948.3966@i88.isc.com>
Date: 26 Mar 91 02:39:48 GMT
References: <95@fbits.ttank.com>
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In article <95@fbits.ttank.com> Mariusz@fbits.ttank.com (Mariusz Stanczak) writes:
>No offence to the Subject, but I just finished "reading" 
>an interesting article in Electronic Design (USSN 0013-4872,
>Vol 39, No. 5, March 14 1991, page 59) entitled Upgrade a
>68030-Based System With a Clever Cache Design.
>The article outlines how to build and add to an existing
>system (i.e. no changes to architecture) a cache controller
>doughterboard with 5 chips (two cache comparators and three
>PALs) plus 8 static RAM chips that (on the 68030) gives
>a theoretical 29% speedup.  I can bearly follow traces, and
>read signal names, but it appears that all (similar ;-))
>signals that this project uses are on the 68010, SO maybe
>the brave-at-heart-hardware-types would be interested at
>looking into the feasibility of transfering the idea to the
>3B1 hardware?  Involved project no doubt, but if possible,
>it'd be a safe way to boost performance of the system (as
>opposed to trying to fit a more efficient processor and
>making the OS angry ;-)).
>

  Motorola has an app note that describes how to make a daughter board for
the 68020 to replace a 68000 or 68010, you can also have a 68881/2.  I would
dearly love to make this board, including support for vidpal, but I haven't
had the time.  I just don't have time to do both the kernel mods and the
hardware.
  BTW, the 68020 does have an instruction cache and the app note claims ~ 100%
increase in performance.  If anyone who has access to the code would like to
colaberate I would like the help.

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