Path: utzoo!utgpu!news-server.csri.toronto.edu!torsqnt!lethe!tvcent!comspec!scocan!chance!john
From: john@chance.UUCP (John R. MacMillan)
Newsgroups: comp.sys.3b1
Subject: Re: Hardware freaks Unite (on this one)
Keywords: 3B1, cache, hardware project suggestion.
Message-ID: <1991Mar27.063904.10091@chance.UUCP>
Date: 27 Mar 91 06:39:04 GMT
References: <95@fbits.ttank.com>
Organization: Haphazard
Lines: 13

|...  Involved project no doubt, but if possible,
|it'd be a safe way to boost performance of the system (as
|opposed to trying to fit a more efficient processor and
|making the OS angry ;-)).

Unless the cache is of physical memory and completely transparent the
virtual memory system would have to know about it.  And if that is
the case, you probably wouldn't get as big performance wins because
the physical memory is changing a lot to handle the virtual address
space.

Of course the only way to find out is for one of you folks who know
which end of a soldering iron to hold to try it out... :-)