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From: krowitz@RICHTER.MIT.EDU (David Krowitz)
Newsgroups: comp.sys.apollo
Subject: Re: Snakebytes (long -- and poisonous?).
Message-ID: <9103281525.AA07026@richter.mit.edu>
Date: 28 Mar 91 15:25:48 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Organization: The Internet
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The HP9000 series 700 CPU is a 3-chip set implementing the
PA-RISC architecture (this is the same RISC architecture
used by HP in the 800 series and in their RISC minicomputer
lines). HP did *not* attempt to put the entire CPU on a
single chip for a number of reasons:

1) power disipation -- cramming that much circuitry running
   at that speed onto a single chip would melt the chip. As
   it is, each of the 3 chips is mounted under a massive
   heat sink.

2) Cache size. One of the things which has held back the Intel
   i860 as a CPU chip is the limitted size of the i-cache and
   the d-cache. In addition, on-chip caches make it difficult
   to implement parallel processors due to the difficulty of
   maintaining cache-coherency among the on-chip caches. Not
   that I'm aware of any HP parallel processor plans ... I've
   just watched the problems that Alliant has had in getting
   their FX2800 (28 i860's running in a shared-memory parallel
   processor) to run at it's maximum potential speed.

To answer your question directly, there is no on-chip cache ...
it's all external, but their is no penalty since the system
was designed as a multi-chip CPU. As with all CPU's, accessing
data in a register (the ultimate on-chip cache) is always faster
than accessing data in the memory, cache or otherwise, because
you can eliminate a load/store instruction. The new LAPACK linear
algebra libraries are explicitly designed around this principle
and run a *lot* faster than LINPACK/EISPACK.


 -- David Krowitz

krowitz@richter.mit.edu   (18.83.0.109)
krowitz%richter.mit.edu@eddie.mit.edu
krowitz%richter.mit.edu@mitvma.bitnet
(in order of decreasing preference)