Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!pacbell.com!ucsd!ucrmath!rhyde
From: rhyde@ucrmath.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: AE Rumors
Message-ID: <13033@ucrmath.ucr.edu>
Date: 25 Mar 91 02:11:30 GMT
References: <1991Mar24.091116.27945@mthvax.cs.miami.edu> <13028@ucrmath.ucr.edu> <1991Mar24.203009.2055@m.cs.uiuc.edu>
Organization: University of California, Riverside
Lines: 43

It's too bad all of these posts aren't saved up some place convenient (like
they do on BIX and CompuServe).  That way I could post a pointer rather than
explaining bus interfaces every month!

>>>>
   Uhh, last time I checked, 33MHz '386s used 80ns RAM.  There's a thing
called a "cache" that interfaces high-speed CPUs and slow memory.
The GS accelerators have one.  You put it together and figure it out.
<<<<

The 65xxx family has always used a two-phase clock and a high performance
bus interface.  X Mhz on a 65xxx is comparable to 2X Mhz on most other
processors (at least, in terms of memory access times).  A 25Mhz 65c816
(on the bus anyway) is comparable to a 80386 running at 50Mhz (please, no
flames or jumping for joy, the performance of the two is not the same for
reasons I'll soon get in to).  Indeed, the two-phase clock is assymmetrical,
so memory access time is even faster than this.  You need less than 20ns
chips for a 25Mhz part.  Yes, static RAMs exist which run this fast.  They
are very expensive.  The 386/486/68040 etc., have another big advantage,
the cache is on the microprocessor chip.  Even the ZIP chip folks aren't
doing exactly this (If I understand how their circuit works).  They use a
hybrid approach).  The end result is that you also need decoding and cache
support circuitry. This steals some of those precious ns away.  Now you're
talking 5-10 ns RAM.  Yes, it exists, but it is *very* expensive.
Most off-processor caches on 386 systems do *not* provide true zero wait
states.  They let you get by with one wait state rather than several.
Processors like the 386 don't slow down as much for some number of wait
states because they can fetch four bytes with one wait state penalty (compared
to the 816 fetching one byte with a wait state penalty).
Comparing the two on a cycle by cycle basis is very difficult and complex,
but a simplification that might be valid is to say that a waitstate hurts the
65c816 about 4-8 times as much as it hurts the 80386.  For example, introducing
*just one* wait state to the 65c816 almost cuts the speed of the executed code
in half.  One wait state on on a 386 doesn't hurt anywhere near as much.

True, accelerators on the GS (and below!) have a cache, but they're not
running at 25Mhz either!  The best I've seen is a butchered TWGS running
at about 12 Mhz.  It required 15 ns RAM.

Wet Dream: WDC produces a 12.5 Mhz 65032 (with 32-bit bus interface) and
Apple builds a machine around it.  Such a device would probably compete
fairly with 16 & 20 Mhz 68020 machines.  A fast '816 with its 8-bit bus
doesn't really stand a chance.