Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!ucsd!ucbvax!hplabs!hpda!hpcuhb!hpcuhe!linley
From: linley@hpcuhe.cup.hp.com (Linley Gwennap)
Newsgroups: comp.arch
Subject: Re: Snakebytes (long -- and poisonous?).
Message-ID: <32580009@hpcuhe.cup.hp.com>
Date: 29 Mar 91 00:36:34 GMT
References: <1998@kuling.UUCP>
Organization: PA-RISC Marketing Central
Lines: 11

(Anand Iyengar) asks
>Cache: 128 kB instr/256 kB data (720, 730), 256 kB instr/256 kB data.
	Are these external caches (sound too big to be on chip)?  How much
(if any) delay does a cache access cost?  
----------
The caches on the Series 700 are all implemented external to the chip
using standard commercially available SRAMs.  There is no delay for a
cache access; so long as the cache is hit, instructions execute one
per clock cycle.
						--Linley Gwennap
						  Hewlett-Packard