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From: devine@shodha.enet.dec.com (Bob Devine)
Newsgroups: comp.arch
Subject: Re: Memory hierarchy
Summary: summary
Message-ID: <2845@shodha.enet.dec.com>
Date: 29 Mar 91 23:28:26 GMT
References: <1998@kuling.UUCP> <2832@shodha.enet.dec.com> <1991Mar28.152952.18380@rice.edu>
Organization: Digital Equipment Corp. - Colorado Springs, CO.
Lines: 19

I asked:
> My questions are to the folks with a /dev/crystal_ball: when will
> two level processor caches be here?  When will a storage hierarchy
> be extended to disks (or to ram-disk, or ... etc)?

Several folks have sent mail answering the first question by telling
me that some current generation and near-future processors will
have two level caches (eg, MIPS R6000, some Intel 486s, future Moto
68040, and future SPARC chips were mentioned).  Thanks!

However, the point I would like to make is that the processors are
beating the rest of the system for performance.  Many problems
that were cpu-bound are now I/O bound or have bottlenecks that moved.
The basic cpu/memory/disk hierarchy has been expanding so that at
each of the interfaces more levels will be used.  There are a few
companies that are looking at the storage issues but no revolutionary
proposal has emerged -- news on that was what I was fishing for...

Bob Devine