Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!mash From: mash@mips.com (John Mashey) Newsgroups: comp.arch Subject: Re: Segmented Architectures ( formerly Re: 48-bit computers) Message-ID: <1654@spim.mips.COM> Date: 30 Mar 91 22:57:47 GMT References: <1991Mar27.172325.10800@sj.nec.com> <1991Mar29.011956.2801393@locus.com> Sender: news@mips.COM Organization: MIPS Computer Systems, Inc. Lines: 30 Nntp-Posting-Host: winchester.mips.com In article <1991Mar29.011956.2801393@locus.com> dana@locus.com (Dana H. Myers) writes: ... > The segmented vs. linear addressing architecture argument is moot. >Changes in the 80386 allow one to effectively ignore the segments and >use linear addresses. > > System V/386 does this, AIX-PS/2 does this, etc. > > Further overzealous condemnation of Intel CPUs is pointless and >rhetorical, especially given that Intel has left the segmented architecture >behind in the 1980's. The 80860 and 80960 are, functionally speaking, not >segmented machines. Well, not quite. People shifted to 32-bit flat as soon as they could on the 386/486, but the chips clearly include a 48-bit (16+32) segmented address scheme as well. Here are a few interesting questions: 1) Does any software in common use actually make use of the segmentation to get significantly more than 32-bit addresses? (i.e., I mean more than, perhaps, dedicating a segment to code and one to data, and maybe one to stack? [I hope to get answers to this one.] 2) The 586 is reputed to be a 64-bit architecture. Does this mean that the 16+32 scheme is abandoned, or that it is inclued along with >32-bit flat addressing? [I don't expect an answer on that; it is an interesting question.] -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems MS 1/05, 930 E. Arques, Sunnyvale, CA 94086