Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!samsung!know!news.cs.indiana.edu!ux1.cso.uiuc.edu!usenet From: mcdonald@aries.scs.uiuc.edu (Doug McDonald) Newsgroups: comp.arch Subject: Re: Coprocessors Message-ID: <1991Mar31.025146.3531@ux1.cso.uiuc.edu> Date: 31 Mar 91 02:51:46 GMT References: <1991Mar27.123720.3992@decvax.dec.com> <2892@megatek.megatek.uucp> <10501@exodus.Eng.Sun.COM> Sender: usenet@ux1.cso.uiuc.edu (News) Organization: University of Illinois at Urbana Lines: 23 >|> In <2892@megatek.megatek.uucp> mark@megatek.UUCP (mark thompson) >|> writes: >|> >|> >Whenever I read architecture manuals for (eg. the Moto 68000 series), >|> >they invariably support several coprocessors. Also invariably, one of >|> >those coprocessors is for floating point. >|> ... >|> >Has anyone tried to do something wonderful with one of the undedicated >|> >coprocessors, examples of wonderful being I/O channel controllers or a >|> >business instruction set? >|> > Certain LSI PDP-11 had (have?) business coprocessors that work with them. Certain other DEC LSI cpus (i.e. VAX) have the business instructions, or some of them, emulated in software, because it was faster :-). I doubt that that a business instruction set has quite the regularity of the major part of a FPU. Doug McDonald