Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!uwm.edu!linac!att!cbnewsh!wcs
From: wcs@cbnewsh.att.com (Bill Stewart 908-949-0705 erebus.att.com!wcs)
Newsgroups: comp.arch
Subject: Re: Snakebytes (long -- and poisonous?).
Message-ID: <1991Mar31.233202.27988@cbnewsh.att.com>
Date: 31 Mar 91 23:32:02 GMT
References: <1998@kuling.UUCP> <32580009@hpcuhe.cup.hp.com>
Organization: AT&T Bell Labs Special Services Division
Lines: 18

In article <32580009@hpcuhe.cup.hp.com> linley@hpcuhe.cup.hp.com (Linley Gwennap) writes:
] > Cache: 128 kB instr/256 kB data (720, 730), 256 kB instr/256 kB data.
] > Are these external caches (sound too big to be on chip)?  How much
] > (if any) delay does a cache access cost?  
] The caches on the Series 700 are all implemented external to the chip
] using standard commercially available SRAMs.  There is no delay for a
] cache access; so long as the cache is hit, instructions execute one
] per clock cycle.

Are you saying LOAD and STORE instructions take 1 cycle? !??!
I thought the 700 took 2-4 cycles, like most machines.
Can you at least overlap loads and stores if you use separate
registers, for applications like bcopy()?
-- 
# Bill Stewart 908-949-0705 erebus.att.com!wcs AT&T Bell Labs 4M-312 Holmdel NJ
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