Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!elroy.jpl.nasa.gov!ames!haven!decuac!grebyn!ckp
From: ckp@grebyn.com (Checkpoint Technologies)
Newsgroups: comp.arch
Subject: Re: Segmented Architectures ( formerly Re: 48-bit computers)
Message-ID: <1991Apr1.045051.3220@grebyn.com>
Date: 1 Apr 91 04:50:51 GMT
References: <1991Mar27.172325.10800@sj.nec.com> <00670208556@elgamy.RAIDERNET.COM>
Organization: Grebyn Timesharing
Lines: 14

Suppose you took a machine with a very large pointer; 32 bits will do
for arguments' sake, but you could imagine this with 48 or 64 if you
like.  Then let's say the operating system permits an application to
have a sparse virtual address space.  Then applications could choose
some number of upper address bits and designate those as "segment
numbers", and the rest of the bits as "offset".

Now, what significant differences exist between this and a "real"
segmented machine?  I can't think of any offhand...
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