Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!mash From: mash@mips.com (John Mashey) Newsgroups: comp.arch Subject: Re: memory management implementations Message-ID: <1726@spim.mips.COM> Date: 2 Apr 91 04:27:55 GMT References: Sender: news@mips.COM Organization: MIPS Computer Systems, Inc. Lines: 26 Nntp-Posting-Host: winchester.mips.com In article jonathan@cs.pitt.edu (Jonathan Eunice) writes: >My impression is that most workstations, and perhaps a fair number of >other systems as well, use some low-cost approximation of the LRU >algorithm--such as a variation on the Clock algorithm--for page >replacement. (If this is wrong, let me know.) >Are the LRU approximations used "good enough?" That is, with all of >the transistors we can now put on a chip or multi-chip CPU, does it >make sense to use more expensive, closer-to-true-LRU algorithms? >Would this help VM performance some measurable amount, and is it >reasonable to do? What is the real-estate/transistor-count cost? >What is the design/opportunity costs? I don't recall the exact numbers, but I recall that the effect was: 1) If you have 2-set-associative TLB, LRU is important, and has a better miss rate than random replacement, and is cheap to do. 2) as the degree of associativity rises, the difference between LRU and random mostly disappears; the cost for implementing LRU may go up; the cost to implement random is minimal. maybe somebody can cite some references. -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems MS 1/05, 930 E. Arques, Sunnyvale, CA 94086