Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!elroy.jpl.nasa.gov!sdd.hp.com!hplabs!hpfcso!cag
From: cag@hpfcso.FC.HP.COM (Craig Gleason)
Newsgroups: comp.arch
Subject: Re: Snakebytes (long -- and poisonous?).
Message-ID: <8840022@hpfcso.FC.HP.COM>
Date: 2 Apr 91 01:14:30 GMT
References: <1998@kuling.UUCP>
Organization: Hewlett-Packard, Fort Collins, CO, USA
Lines: 27

>(Anand Iyengar) asks
>>Cache: 128 kB instr/256 kB data (720, 730), 256 kB instr/256 kB data.
>	Are these external caches (sound too big to be on chip)?  How much
>(if any) delay does a cache access cost?  
>----------
>The caches on the Series 700 are all implemented external to the chip
>using standard commercially available SRAMs.  There is no delay for a
>cache access; so long as the cache is hit, instructions execute one
>per clock cycle.
>						--Linley Gwennap
>						  Hewlett-Packard

This isn't strictly true.  All loads and I-fetches take one cycle.  There
is a load-use penalty of one cycle when the instruction after the load
uses the load data as an operand.

Stores take three cycles on the data cache, but if they are followed by
non-data cache accesses, there will be no penalty.  Therefore the store
penalty can be zero, one or two states, and the compilers can schedule
accordingly. 

The processor was optimized for loads/I-fetches since the biggest performance
lever is processor frequency.  Slowing down to allow a one or two cycle store
would not have been a good performance tradeoff.

Craig Gleason
Hewlett-Packard