Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!sdd.hp.com!hplabs!hpcc05!hpcuhb!hpcuhe!linley
From: linley@hpcuhe.cup.hp.com (Linley Gwennap)
Newsgroups: comp.arch
Subject: Re: Snakebytes (long -- and poisonous?)
Message-ID: <32580012@hpcuhe.cup.hp.com>
Date: 1 Apr 91 23:51:18 GMT
References: <1996@kuling.UUCP>
Organization: PA-RISC Marketing Central
Lines: 51

I'd like to take a moment to respond to comments that the Series 700
has achieved its high performance due primarily to high (66 MHz) clock
frequencies resulting from advanced CMOS processes.  While HP's IC
processes are as good as anyone's, the Series 700 CPU is implemented
in a 1.0 micron, 3-metal-layer CMOS process which is pretty standard
throughout the industry.  It is nearly identical to IBM's 1.0 micron
process used in their 20-30 MHz RS/6000s, and not as dense as the
0.8 micron process used in IBM's 41 MHz Model 550.

TUTORIAL MODE ON:

The cycle time of a CPU is determined by the longest amount of time
required to complete a single pipeline stage.  This in turn is driven
by the number of gate delays, the length of the gate delay, the number
of chip crossings, and the length of time to cross between chips.  Of
these factors, only the length of the gate delay is determined directly
by the IC process.

The number of gate delays is determined by the number of pipeline
stages and the complexity of the design (and of course the skill of
the designer).  The R4000 uses a longer (8-stage) pipeline to reduce
the number of gates needed for a single stage and thus reduce the
cycle time.  The Series 700 focused on reducing the complexity of
the design to achieve a fast cycle time.  The RS/6000 is not focused
on cycle time at all, resulting in a complex design and a relatively
slow clock frequency.

The RS/6000 also suffers from the chip crossing problem.  The complex
superscalar design requires 8 chips to implement instead of 3 on the
Series 700, forcing signals to move from chip to chip in a single
clock cycle.  This additional overhead further slows the RS/6000 clock.
To improve its clock frequency, IBM must either (a) use a denser
IC process to cram more circuitry onto a smaller number of chips;
(b) use a multi-chip module to reduce chip crossing delays; or (c)
simplify the America design by eliminating some of the superscalar
complexities.

Of course, cycle time in itself does not determine CPU performance,
but that is a different discussion.

TUTORIAL MODE COMPLETE

In conclusion, the Series 700 uses a simple, efficient processor
design, coupled with state-of-the-art IC processes, to achieve high
clock frequencies and high performance.  HP's 1.0 micron IC process
has as much room to evolve as other vendors' processes, and more
headroom than IBM's 41 MHz RS/6000.  The Series 700 family will
continue to improve in performance as IC processes improve.

						--Linley Gwennap
						  Hewlett-Packard