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From: niehaus@tempo.cs.umass.EDU (Douglas Niehaus)
Newsgroups: comp.arch
Subject: Branch Delay Slots and Main Memory
Message-ID: <28677@dime.cs.umass.edu>
Date: 2 Apr 91 15:25:03 GMT
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Reply-To: niehaus@tempo.cs.umass.EDU (Douglas Niehaus)
Organization: University of Massachusetts-Amherst
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Ok, so I am reading the RS2000 book by Kane, and I have felt like I understood
what was going on, but I have a nagging question left.

Branch delay iand load delay slots are one instruction in length, which I can deal with as long
as what is being fetched from memory is in the cache, but what happens for a cache miss?

I can deduce, I think, that on a miss the who processor must get frozen until the 
fetch from main memory is finished, or else the single delay slot would not be enough.
Is this correct? If not, what DOES happen? If so, just how is it done?

Douglas Niehaus
niehaus@tempo.cs.umass.edu