Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!rpi!uupsi!grebyn!ckp
From: ckp@grebyn.com (Checkpoint Technologies)
Newsgroups: comp.arch
Subject: Re: Segmented Architectures ( formerly Re: 48-bit computers)
Message-ID: <1991Apr2.185644.4920@grebyn.com>
Date: 2 Apr 91 18:56:44 GMT
References: <00670208556@elgamy.RAIDERNET.COM> <1991Apr1.045051.3220@grebyn.com> <1991Apr1.154918.8342@granite.ma30.bull.com>
Organization: Grebyn Timesharing
Lines: 27

In article <1991Apr1.154918.8342@granite.ma30.bull.com> kittlitz@granite.ma30.bull.com (Edward N. Kittlitz) writes:
>Segments give you access control. The 386 will
>let you put multiple segments within one page, each with differing
>differing access rights. I believe that such an architecture may
>provide a convenient way for implementing protected object-oriented systems.
>It would be better if they had a TLB instead of the one per segment-register
>'shadow registers'/descriptor cache. (I must admit I don't know if
>there is a TLB in the 486.)

I don't think that "Segments give access control" is a general statement
about segments; I think Intel chose to use Segments as the machanism
which provides access control.  Other systems use access bits in the
page tables to provide the same thing.

Systems with conventional page tables (not inverted) can permit the same
physical memory to appear in multiple separate virtual addresses to the
same process, or to separate processes, with different access rights in
each case.  I understand that inverted page tables make this more
difficult but not impossible.

And no, I don't believe the 486 has a TLB for the segment descriptor
cache.  It has a TLB for the page tables though, as the 386 does.
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