Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!uunet!littlei!intelhf!ichips!ichips!glew From: glew@pdx007.intel.com (Andy Glew) Newsgroups: comp.arch Subject: Re: Segmented Architectures ( formerly Re: 48-bit computers) Message-ID: Date: 2 Apr 91 15:19:37 GMT References: <1991Mar27.172325.10800@sj.nec.com> <00670208556@elgamy.RAIDERNET.COM> <1991Apr1.045051.3220@grebyn.com> <1991Apr1.154918.8342@granite.ma30.bull.com> Sender: news@omews63.intel.com (News Account) Organization: Intel Corp., Hillsboro, Oregon Lines: 23 In-Reply-To: kittlitz@granite.ma30.bull.com's message of 1 Apr 91 15:49:18 GMT Segments give you access control. The 386 will let you put multiple segments within one page, each with differing differing access rights. I believe that such an architecture may provide a convenient way for implementing protected object-oriented systems. It would be better if they had a TLB instead of the one per segment-register 'shadow registers'/descriptor cache. (I must admit I don't know if there is a TLB in the 486.) To avoid confusion: the i486 processor has a TLB. 4 way set associative, 8 sets. For that matter, so does the i386. The TLB, however, stores page-oriented protection information. Another, additional, mechanism is used for segments. -- --- Andy Glew, glew@ichips.intel.com Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124-6497 This is a private posting; it does not indicate opinions or positions of Intel Corp.